(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate for a liquid crystal display and a method for fabricating the same and, more particularly, to a TFT array substrate that can be fabricated through simplified processing steps while ensuring good performance characteristics.
(b) Description of the Related Art
Generally, a liquid crystal display (LCD) is formed with two glass substrates, and a liquid crystal sandwiched between the substrates.
One of the substrates has a common electrode, a color filter and a black matrix, and the other substrate has pixel electrodes and thin film transistors (TFTs). The former substrate is usually called the xe2x80x9ccolor filter substrate,xe2x80x9d and the latter substrate called the xe2x80x9cTFT array substrate.xe2x80x9d
In a liquid crystal display, lower resistance materials such as aluminum or aluminum alloy are commonly used for wiring lines in order to prevent signal transmission delays. However, in the TFT array substrate, a transparent conductive material such as indium tin oxide (ITO) is used to form pixel electrodes or to reinforce pad portions. However, ITO shows very poor contact characteristic with respect to the aluminum-based material. In this respect, a separate material should be provided between the ITO and the aluminum-based material, and in the pad portions, the aluminum-based material should be removed to prevent corrosion thereof. This involves complicated processing steps. Furthermore, when an aluminum-based layer contacts a silicon-based semiconductor layer, the aluminum content tends to be diffused through the semiconductor layer. In order to solve such a problem, it is required that a separate layer based on other metallic material should be provided between the aluminum-based layer and the silicon-based layer. This requires a multiple-layered structure having different etching conditions.
On the other hand, the TFT array substrate is usually fabricated through photolithography based on a plurality of masks. In order to reduce the production cost, the number of masks should be reduced while obtaining the same or better performance characteristic of the device.
It is an object of the present invention to provide a TFT array substrate, and a method for fabricating the TFT array substrate that involves good contact characteristics while bearing wiring lines with lower resistance.
It is another object of the present invention to provide a method for fabricating a TFT array substrate that involves simplified processing steps.
These and other objects may be achieved in the following way.
A conductive layer connected to an aluminum-based layer is formed of indium zinc oxide (IZO), and a chrome based layer interposed between the aluminum-based layer and a semiconductor layer is patterned through dry etching.
Specifically, in a method for fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to thereby form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer, and a semiconductor layer are sequentially formed on the substrate with the gate line assembly. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to thereby form a data line assembly. At this time, the under-layer of the conductive film is patterned through dry etching. The data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines, and drain electrodes separated from the source electrodes while interposing the gate electrodes. A protective layer is deposited onto the substrate, and patterned to form first contact holes over the drain electrodes. Pixel electrodes are formed on the protective layer while electrically connected to the drain electrodes.
The pixel electrodes are formed with a transparent conductive material such as IZO. The under-layer of the conductive film has a thickness of 300 xc3x85 or less. The dry etching gas for etching the under-layer of the conductive film contains Cl2 or HCl.
The gate line assembly further includes gate pads receiving scanning signals from the outside and transmitting the scanning signals to the gate lines. The data line assembly further includes data pads receiving picture signals from the outside and transmitting the picture signals to the data lines. The protective layer is further provided with second and third contact holes exposing the data pads, and the gate pads together with the gate insulating layer. Subsidiary gate and data pads are formed at the same plane as the pixel electrodes while being electrically connected to the gate and data pads through the second and third contact holes.
The data line assembly and the semiconductor layer are formed together through photolithography using photoresist patterns being partially differentiated in thickness. The photoresist patterns include a first pattern with a predetermined thickness, a second pattern with a thickness smaller than the thickness of the first pattern, and a third pattern with no thickness. The first photoresist pattern is placed over the data line assembly, and the second photoresist pattern is placed between the source and drain electrodes. The thickness of the second photoresist pattern is established to be one half or less of the first photoresist pattern.
The photoresist patterns are made using a mask. The mask has a first region with a predetermined light transmission, a second region with a light transmission lower than the light transmission of the first region, and a third region with a light transmission higher than the light transmission of the first region.
The mask is provided with a semi-transparent film or a slit pattern with a slit size smaller than the decomposition capacity range of light exposure to control the light transmission of the first to third regions in a different manner.
An ohmic contact layer may be provided in-between the semiconductor layer and the data line assembly. The data line assembly, the ohmic contact layer and the semiconductor layer may be patterned using one mask. In this case, the under-layer of the conductive film, the ohmic contact layer and the semiconductor layer are continuously patterned through dry etching.